1. Field of the Invention
The present invention relates to a solid state imaging apparatus and a manufacturing method for the same. More particularly, the present invention relates to a solid state imaging apparatus with transistors having different film thickness of gate insulating films and a manufacturing method for the same.
2. Description of the Related Art
A solid state imaging apparatus using a charge coupled device (CCD) is known as a typical example of the solid state imaging apparatus. FIG. 1 shows the well known CCD solid state imaging apparatus of an interline transfer system.
Referring to FIG. 1, the imaging apparatus is composed of an imaging section 101, a horizontal CCD section 102 extending in a horizontal direction and an output section 103 as a charge detecting section. The imaging section 101 is composed of a plurality of photodiodes (photoelectric converting elements) 104 arranged in a 2-dimensional matrix manner to convert a light signal into a signal charge through photoelectric conversion and to store the signal charge.
Further, a vertical CCD section 105 is adjacent to a column of the photodiodes 104 to transfer the signal charge in a vertical direction. A read section 106 is provided between the photodiode 104 and the vertical CCD section 105 to read the signal charge. A remaining section of the imaging section 101 other than the above-described portions is an element separating region 107.
Such an imaging apparatus operates as follows. That is, a signal charge is stored through photoelectric conversion by the photodiode 104 for a predetermined time and is read out by the vertical CCD section 105 through the read section 106. After being read out to the vertical CCD section 105, the signal charge is transferred to the vertical direction for the horizontal CCD section 102 one line by one line. After being transferred to the horizontal CCD section 102, the signal charge is transferred to the horizontal direction in the horizontal CCD section 102, and is detected as an output voltage by the output section (charge detecting section) 103.
The output section 103 is composed of a detection capacitor as a floating diffusion layer capacitor and an output amplifier which is connected with the detection capacitor. From the viewpoint of impedance conversion, a source follower grounding circuit type amplifier of 2 stages or 3 stages and composed of MOS transistors is used as the output amplifier in many cases. The source follower grounding circuit type amplifier is referred to as a source follower type amplifier, hereinafter.
FIG. 2 schematically shows the floating diffusion layer capacitor as a detection capacitor 108 and a 3-stage source follower amplifier 109 connected with the detection capacitor. A signal charge is transferred in the horizontal CCD section 102 (not shown in FIG. 2), and is stored into the floating diffusion layer capacitor 108. The potential change at this time is transmitted to the transistors in the subsequent stage through a driver transistor D101 in FIG. 1 in the initial stage of the amplifier. Then, the potential change is outputted from an output terminal Vout.
In this case, the driver transistors are the transistors D101, D102 and D103 in the source follower type amplifier. In the driver transistor, the source side is connected with a higher potential power supply Vdd. The transistors L101, L102 and L103 in which the drains are grounded are called load transistors. Moreover, sets of transistors D101 and L101, D102 an L102, and D103 and L103 are called the first stage of the amplifier, the second stage, and the third stage, respectively, from the input side to which the floating diffusion layer capacitor 108 is connected. In each set, the drain of the driver transistor and the source of the load transistor are connected with each other.
FIGS. 3A and 3B show cross sectional structure of the transistor of the output amplifier. FIGS. 3A and 3B show the cross sectional structures of the transistors of the first stage of the amplifier and the second or third stage of the amplifier, respectively. A P-type well 111 is formed on an N-type substrate 110, and the transistor has a source region 112 and drain region 113 which are formed in P-type well 111 as high concentration N-type impurity regions. A gate electrode 115 is formed on the channel between the source region 112 and the drain region 113 through a gate insulating film 114 having the film thickness from about 70 nm to about 85 nm. Thus, the transistor is formed.
The channel lengths of the transistors are illustrated in FIGS. 3A and 3B to equal to each other. However, the channel length is different depending on whether the transistor is the driver transistor or the load transistor. Moreover, the channel length is different depending on whether the transistor is in the first stage, the second stage or the third stage. In FIGS. 3A and 3B, it should be noted that these transistors of the amplifier have different channel lengths and different channel widths sometimes but have the same structure in the vertical direction.
FIG. 4 shows a cross sectional view of the first stage transistor of the amplifier and the horizontal CCD section 102 in a charge transfer direction from the floating diffusion layer to a reset. The horizontal CCD section 102 is formed on an N-type embedded channel 116 as the charge transfer channel which is formed in the P-type well 111 on the N-type substrate 110. Also, the horizontal CCD section 102 has the charge transfer electrode formed of a polysilicon film through the gate insulating film 114. The gate insulating film 114 is sometimes composed of a multiple film (ONO film) in which an oxide film (SiO2) is formed in the either side of a nitride film (Si3N4). Also, the charge transfer electrode is sometimes formed of 2 polysilicon films.
The detection capacitor 108 as the floating diffusion layer capacitor is formed at an end portion of the horizontal CCD section 102 through the output gate OG. A high concentration N-type impurity layer is formed such that the signal charge stored in detection capacitor 108 can be taken out through a contact. A positive potential is given to a reset electrode xcfx86R after the charge detection, so that the signal charge is discharged to the reset drain 117. Also, the potential of the floating diffusion layer is reset.
On the other hand, a drive transistor of an amplifier in the output section is formed as a MOS (Metal Oxide Semiconductor) type transistor. Each transistor has a drain region 113 and a source region 112 of high concentration N-type impurity regions formed in opposing positions of a P-type well 111 on an N-type substrate 110. A gate electrode 115 of a polysilicon film is formed through a gate insulating film 114. It should be noted that although not illustrated in FIG. 4, the vertical CCD section 105 has substantially the same structure as that of the horizontal CCD section 102.
FIGS. 5A-1 and 5A-2 to 5D-1 and 5D-2 show the processes in the manufacturing method of the conventional solid state imaging apparatus. The figures with xe2x80x9cxe2x88x921xe2x80x9d show the processes of the manufacturing method of the amplifier transistor of the first stage, and the figures with xe2x80x9cxe2x88x922xe2x80x9d show the processes of the manufacturing method of the amplifier transistor of the second or third stage. The processes of the figures with xe2x80x9cxe2x88x921xe2x80x9d are completely the same processes of the figures with xe2x80x9cxe2x88x922xe2x80x9d. As mentioned above, in the conventional solid state imaging apparatus, all of these amplifier transistors have the same structure.
As shown in FIGS. 5A-1 and 5A-2, the P-type well 111 is first formed on the N-type substrate 110 and then the gate insulating film 114 is formed. An N-type embedded channel is already formed in a region where the vertical CCD and the horizontal CCD should be formed, although not illustrated. When an ONO film is used for the gate insulating film, the multiple film which is composed of an oxide film, a nitride film and an oxide film is formed in order.
Next, as shown in FIGS. 5B-1 and 5B-2, the electrode film 120 is formed of a polysilicon film through a gate insulating film 114.
Next, as shown in FIGS. 5C-1 and 5C-2, a patterning method and an etching method for a photolithography method are applied to form the gate electrode 115.
Next, as shown in FIGS. 5D-1 and 5D-2, an ion implanting method of high concentration N-type impurities is performed in self-alignment with the gate electrode 115 to forming the source region 112 and the drain region 113. Thus, the MOS type transistors are completed.
Through the above processes, the conventional solid state imaging apparatus is manufactured.
Next, the floating diffusion layer capacitor and the structure of the amplifier transistor will be described in detail. How the detection sensitivity when a signal charge is converted into a signal voltage is determined will be described from the relation between the floating diffusion layer capacitor 108 as the detection capacitor in the output section and a gain of the output amplifier. The detection sensitivity is the conversion efficiency that the signal charge is converted into the voltage. Thus, as the efficiency becomes higher, the larger output voltage can be obtained. Therefore, there is a problem in how the detection sensitivity (charge-voltage conversion efficiency) is increased.
When it is supposed that the detection capacitor is Cfj (fF) and the gain of the output amplifier is g, the detection sensitivity Sen (xcexcV/e) is expressed by the following equation (1).
Sen=qxc3x97g/Cfjxe2x80x83xe2x80x83(1)
where q is a charge of an electron. It could be understood from the equation (1) that the detection sensitivity can be improved when the detection capacitor Cfj becomes smaller, or when the gain g becomes larger.
Such a detection capacitor Cfj will be considered. The detection capacitor Cfj is composed of the base PN junction capacitor C1 of the floating diffusion layer shown in FIG. 4. Recently, however, the base capacitor has been reduced and the influence of the base capacitor to the whole is decreased rather than previously. The influence of capacitors such as wiring capacitor C2 and other parasitic capacitors C3 and C4 becomes large. A relatively large one of such capacitors is the gate capacitor C3 of the amplifier transistor of the first stage. For this reason, to decrease the detection capacitor Cfj, it is necessary to decrease the gate capacitor of the amplifier transistor of the first stage, in addition to the other capacitors. In order to decrease the gate capacitor C3, it is sufficient that the gate width W of the amplifier transistor is made small such that the capacitor width can be made small.
However, there is a limit in the decrease of the gate width W of the amplifier transistor. In order to maintain the characteristic of the amplifier transistor, the width of the amplifier transistor is decreased while the ratio (W/L) of the gate width W to the gate length L is maintained. In this case, however, when the gate length L becomes smaller than about 3 xcexcm, the short channel effect occurs. Thus, the expected transistor characteristic cannot be obtained. Therefore, it is difficult to further decrease the width or length.
On the other hand, with the amplifier gain, the optimization of the sizes of the transistors of the amplifier has been already performed. Therefore, a further higher gain cannot be simply attained. This is because the gate insulating film used for the amplifier transistor is the same as the gate insulating film used for the vertical and horizontal CCD transfer channels in which the transfer efficiency is important.
With the gate insulating film on the CCD transfer channel, the transfer efficiency is generally degraded when the film thickness of the gate insulating film is made thin. Therefore, the gate insulating film is necessary to have the film thickness of some degree. This film thickness is approximately in a range of 70 nm to about 85 nm. Therefore, if the film thickness of the gate insulating film is made thin, the transconductance gm of the amplifier transistor and the amplifier gain can be improved. Conventionally, the gate insulating film of the transfer electrode had priority for the higher transfer efficiency.
In conjunction with the above description, a solid state imaging apparatus is described in Japanese Laid Open Patent application (JP-A-Heisei 3-192766). In this reference, the imaging apparatus is composed of photoelectric conversion means provided on the surface of a semiconductor substrate. Signal charge transfer means transfers a signal charge produced by the photoelectric conversion means. An output amplifier detects the signal charge transferred by the signal charge transfer means as a voltage change of a signal detection capacitor which is provided on the surface of the semiconductor substrate and outputs a signal voltage corresponding to the detected voltage change. A conductive film is provided between the signal detection capacitor and the surface of the semiconductor substrate and is supplied at the end with an output signal of the output amplifier.
Also, a CCD solid state imaging apparatus is described in Japanese Laid Open Patent application (JP-A-Heisei 4-369187). In this reference, a signal charge from the final stage of the charge transfer section 2 composed of a CCD is once stored in a floating diffusion FD via an output gate OG. A voltage change xcex94V due to the stored charge is supplied to a source follower circuit 5, so that an image signal S is taken out from the output terminal xcfx86out of the source follower circuit in an output section 1. An output side of the source follower circuit 5 is connected with the output gate OG so that the image signal S outputted from the source follower circuit 5 is fed back to the output gate OG.
Also, a CCD solid state imaging apparatus is described in Japanese Laid Open Patent application (JP-A-Heisei 5-63177). In this reference, a signal charge from the final stage of the charge transfer section is stored in a floating diffusion region FD. A voltage change due to the stored charge is supplied to a source follower circuit 5 which is composed of a drive MOS transistor 3 and a load MOS transistor 4. As a result, the signal charge is taken out as an output voltage Vout from the output terminal Tout of the source follower circuit 5. The drive MOS transistor and the load MOS transistor in the source follower circuit 5 are formed in well regions 21 and 22 on a semiconductor substrate, respectively. The impurity density of the well region 21 is different from that of the well region 22.
Therefore, an object of the present invention is to provide a solid state imaging apparatus and a method of manufacturing of the same.
Another object of the present invention is to provide a solid state imaging apparatus having detection sensitivity improved and a method of manufacturing of the same.
Still another object of the present invention is to provide a solid state imaging apparatus having amplifier gain improved and a method of manufacturing of the same.
Yet still another object of the present invention is to provide a solid state imaging apparatus with transistors having different gate insulating film thicknesses and a method of manufacturing of the same.
In order to achieve an aspect of the present invention, a solid state imaging apparatus includes a detection capacitor storing a signal charge, and an output amplifier including a plurality of transistors, and outputting the signal charge stored in the detection capacitor as a voltage signal. A gate of one of the plurality of transistors as an input transistor is connected to the detection capacitor. Also, the plurality of transistors other than the input transistor has a thinner gate insulating film than the input transistor.
The output amplifier preferably is a source follower amplifier circuit.
Also, the output amplifier includes a plurality of stages, each of which includes two of the plurality of transistors as a drive transistor and as a load transistor, and the input transistor is the drive transistor of a first stage of the plurality of stages. In this case, the drive transistors of the plurality of stages other than the first stage may have the gate insulating film thinner than that of the input transistor. Instead, the drive transistors and the load transistors in the plurality of stages other than the first stage may have the gate insulating film thinner than that of the input transistor.
In addition, the solid state imaging apparatus may further include a CCD transfer section having an insulting film and transferring the signal charge to the detection capacity. In this case, a film thickness of the insulating film of the CCD transfer section is substantially the same as that of the gate insulating film of the input transistor. In this case, the insulating film of the CCD transfer section and the gate insulating film of the input transistor may be formed of an ONO film. Instead, the insulating film of the CCD transfer section and the gate insulating film of the input transistor may be formed of an oxide film.
In order to achieve another aspect of the present invention, a method of manufacturing a solid state imaging apparatus include:
partially forming a first gate insulating film and a second gate insulating film in a region for an output amplifier on a semiconductor region of a first conductive type, a film thickness of the first gate insulating film being thicker than that of the second gate insulating film
forming gate electrodes on the first gate insulating film and the second gate insulating film in the region; and
performing ion implantation of impurity ions to complete a plurality of transistors, one of the plurality of transistors as an input transistor having the first gate insulating film and connected to a detection capacitor.
The partially forming a first gate insulating film and a second gate insulating film preferably includes:
forming the first gate insulating film in the region on the semiconductor region;
removing the first gate insulating film from a first region, wherein the region includes the first region and a second region, the input transistor is formed in the second region; and
forming the second gate insulating film in the first region, a film thickness of the second gate insulating film being thinner than the first insulating film. In this case, the forming the second gate insulating film includes thermally oxidizing the semiconductor region. Also, the first gate insulating film is made thicker through the thermal oxidizing.
In addition, the partially forming a first gate insulating film and a second gate insulating film may include:
forming the first gate insulating film as an insulating film of a CCD transfer section.